1. Technical Field
The present invention relates generally to processors and computing systems, and more particularly, to multi-threaded processing systems.
2. Description of the Related Art
Present-day high-speed processors include the capability of simultaneous execution of instructions, speculative fetching of instructions and speculative execution/partial execution of instructions.
In particular, within present-day super-scalar processors, entire program branches may lie within a range of execution from fetching up to just prior to writing final resultant values and groups of instructions whose necessary execution is contingent upon taking a particular program branch may be speculatively loaded and dispatched.
In order to manage such a super-scalar processing system, a completion table is maintained that manages the speculative execution of instructions is included within the processor. The completion table maintains tags that are associated with groups of instructions, so that internal processor elements can determine which groups of instructions have been dispatched. Upon completion or invalidation of instruction groups, the instructions must be flushed from the processor queues.
The above-incorporated patent application describes details of completion table operation and a method and system for implementing flush operations within a processor capable of simultaneously executing multiple threads. A flush table is constructed as register file operations are performed on register file elements to determine which instruction groups to flush in response to flush request indications from various units internal to the processor. However, in order to implement the scheme described in the above-incorporated patent application, logic external to the flush register file is required to perform multiple operations on the flush register file elements in order to determine a flush result that dictates which instruction groups are actually flushed. Either a large external logic is required, or a smaller external logic including multiple clock cycles for performing the required operations is needed.
It is therefore desirable to provide a method and apparatus for determining a flush result that does not require a large external logic circuit or multiple clock cycles.